Yield modeling and BEOL fundamentals
Proceedings of the 2001 international workshop on System-level interconnect prediction
Non-tree routing for reliability and yield improvement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Calibration of Open Interconnect Yield Models
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Yield Improvement by Local Wiring Redundancy
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Robust wiring networks for DfY considering timing constraints
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Closed-form delay and slew metrics made easy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire Sizing for Non-Tree Topology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Resource-constrained timing-driven link insertion for critical delay reduction
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Resource-constrained link insertion for delay reduction
Integration, the VLSI Journal
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Non-tree routing experiences an increasing interest as technology scales into the nanometer range. Via and wire opens have become the main yield detractors considering random spot defects due to the additive manufacturing process of copper wires. Wiring networks containing loops offer some robustness against open defects which increases functional yield. State-of-the-art delay calculation enables the treatment of loops but does not provide an adequate solution for timing analysis in the presence of an open. If the delay in the presence of an open is not properly analyzed, a functional fail will be masked and replaced by a parametric fail which is only detectable applying delay testing. In this paper we present a new method to rapidly calculate the maximum delay if an open occurs in the net. For topologies consisting of non-adjacent loops we provide proof that the worst delay considering the Elmore delay metric can be found in 2N+1 delay calculations, whereas N is the number of loops in the net.