Variational Interconnect Delay Metrics for Statistical Timing Analysis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Considering possible opens in non-tree topology wire delay calculation
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Fast interconnect and gate timing analysis for performance optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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For optimizations like physical synthesis and static timing analysis, efficient interconnect delay and slew computation is critical. Since one cannot often afford to run asymptotic waveform evaluation (Pillage and Rohrer, 1990), constant time solutions are required. This work presents the first complete solution to closed-form formulas for both delay and also for slew. Our metrics are derived from matching circuit moments to the lognormal distribution. From a single table, one can easily implement the metrics for delay and slew for both step and ramp inputs. Experiments validate the effectiveness of the metrics for nets from a real industrial design.