Non-tree routing for reliability and yield improvement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Yield Improvement by Local Wiring Redundancy
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Robust wiring networks for DfY considering timing constraints
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Considering possible opens in non-tree topology wire delay calculation
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Redundant wire insertion for yield improvement
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Asymptotic waveform evaluation for timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computing signal delay in general RC networks by tree/link partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Non-tree routing [VLSI layout]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Under the design experience of a single open on any wiring segment in a signal net, it is known that the non-tree topology for a signal net does not need any adjacent loop. In this paper, based on two time-equivalent splitting operations in a cyclic connection, an accurate transformation-based analysis approach is firstly proposed to compute the timing delays of all the sinks in a non-tree topology without any adjacent loop. Furthermore, given a resource constraint, a 0-1 integer linear programming (ILP) formulation for resource-constrained link insertion is proposed to insert timing-driven geometrical links to reduce the delay of the critical path in a given rectilinear Steiner tree according to the definition of timing-driven redundant links and the design experience of a single open on any wiring segment. For tested Steiner trees, the experimental results show that the 0-1 ILP formulation based on our proposed transformation-based timing analysis has 21.0% and 23.5% of the delay reduction of the critical path under the resource constraints for 10% and 20% of the total wirelength of the original tree in reasonable CPU time on the average, respectively.