Non-tree routing for reliability and yield improvement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Manufacturing-Aware Physical Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Improved multilevel routing with redundant via placement for yield and reliability
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Post-routing redundant via insertion for yield/reliability improvement
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Yield-preferred via insertion based on novel geotopological technology
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Redundant-via enhanced maze routing for yield improvement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Yield Improvement by Local Wiring Redundancy
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Robust wiring networks for DfY considering timing constraints
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Resource-constrained timing-driven link insertion for critical delay reduction
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Resource-constrained link insertion for delay reduction
Integration, the VLSI Journal
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Based on the insertion of internal and external redundant wires into L-type and U-type wires, an efficient two-phase reliability-driven insertion algorithm is proposed to insert redundant wires to construct local cycles and protect the failure of any wire or via for yield improvement. For tested benchmarks, the experimental results show that our proposed insertion approach increases the extra wirelength of internal and external redundant wires by 18.3% and 6.3% to increase the reliability of 56.9% and 5.2% and improve the chip yield by 0.106 and 0.032 on the average in reasonable CPU time, respectively.