Single-layer wire routing and compaction
Single-layer wire routing and compaction
Interchangeable pin routing with application to package layout
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Subwavelength lithography and its potential impact on design and EDA
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Advanced routing in changing technology landscape
Proceedings of the 2003 international symposium on Physical design
Redundant-via enhanced maze routing for yield improvement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Post-routing redundant via insertion and line end extension with via density consideration
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Conjugate conflict continuation graphs for multi-layer constrained via minimization
Information Sciences: an International Journal
Double-via-driven standard cell library design
Proceedings of the conference on Design, automation and test in Europe
Concurrent wire spreading, widening, and filling
Proceedings of the 44th annual Design Automation Conference
Optimal post-routing redundant via insertion
Proceedings of the 2008 international symposium on Physical design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Post-routing redundant via insertion with wire spreading capability
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Redundant via insertion with wire bending
Proceedings of the 2009 international symposium on Physical design
Redundant wire insertion for yield improvement
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Enhanced double via insertion using wire bending
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous redundant via insertion and line end extension for yield optimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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Yield-preferred via insertion is an effective method to reduce the yield loss caused by via failures. The existing methods to apply the redundant-cut vias in metal layers are not efficient nor adequate. In this paper, we present an effective and efficient yield-preferred via insertion method based on a novel geotoplogical layout platform, GEOTOP. Our method chooses the most yield-favored via candidate and insert it into the layout without causing any design rule violations. Experiments with real industry designs show that our method can achieve very high rate of yield-preferred via without increasing the design die size within acceptable running time.