The R*-tree: an efficient and robust access method for points and rectangles
SIGMOD '90 Proceedings of the 1990 ACM SIGMOD international conference on Management of data
Introduction to algorithms
R-trees: a dynamic index structure for spatial searching
SIGMOD '84 Proceedings of the 1984 ACM SIGMOD international conference on Management of data
A Simple via Duplication Tool for Yield Enhancement
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Yield Analysis Methodology for Low Defectivity Wafer Fabs
MTDT '00 Proceedings of the 2000 IEEE International Workshop on Memory Technology, Design and Testing
Improved multilevel routing with redundant via placement for yield and reliability
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Post-routing redundant via insertion for yield/reliability improvement
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Yield-preferred via insertion based on novel geotopological technology
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Redundant-via enhanced maze routing for yield improvement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Is your layout density verification exact?: a fast exact algorithm for density calculation
Proceedings of the 2007 international symposium on Physical design
Post-routing redundant via insertion and line end extension with via density consideration
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Redundant Via Insertion in Restricted Topology Layouts
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Post-routing redundant via insertion with wire spreading capability
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Full-Chip Routing Considering Double-Via Insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and Optimal Redundant Via Insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Redundant via insertion is highly recommended for improving chip yield and reliability. In this paper, we studied the problem of simultaneous double via insertion and wire bending (DVI/WB) in a postrouting stage, where a single via can have at most one redundant via inserted next to it. Aside from this, we are allowed to bend existing signal wires for enhancing the insertion rate of double vias. The primary goal of the DVI/WB problem is to insert as many double vias as possible; the secondary objective is to minimize the amount of layout perturbation. We formulate the DVI/WB problem as that of finding a minimum-weight maximum independent set (mWMIS) on an enhanced conflict graph. We proposed algorithms to perform wire bending and to construct the enhanced conflict graph from a given design. We also proposed a zero-one integer linear program (0-1 ILP)-based approach to solve the mWMIS problem. Moreover, we studied the problem of DVI/WB with the consideration of via density and extended our 0-1 ILP-based approach to solve it. Experimental results show that our approaches can improve the insertion rate by up to 6.34% at the expense of up to 1.29% wirelength increase when compared with the state-of-the-art double via insertion methods that do not consider wire bending. Moreover, when compared with an existing method that considers wire bending, our DVI/WB approach can insert 2% more double vias and produce 32% less wirelength increase rate on average.