Post-routing redundant via insertion with wire spreading capability
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Redundant via insertion with wire bending
Proceedings of the 2009 international symposium on Physical design
Routing for manufacturability and reliability
IEEE Circuits and Systems Magazine
Enhanced double via insertion using wire bending
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal double via insertion with on-track preference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dead via minimization by simultaneous routing and redundant via insertion
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Simultaneous redundant via insertion and line end extension for yield optimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Nanometer-scale standard cell library for enhanced redundant via1 insertion rate
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Non-uniform multilevel analog routing with matching constraints
Proceedings of the 49th Annual Design Automation Conference
Stitch-aware routing for multiple e-beam lithography
Proceedings of the 50th Annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by foundries. Traditionally, double-via insertion is performed at the postlayout stage. The increasing design complexity, however, leaves very limited space for postlayout optimization. It is thus desirable to consider the double-via insertion at both the routing and postrouting stages. In this paper, we present a new full-chip gridless routing system considering double-via insertion for yield enhancement. To fully consider double vias, the router applies a novel two-pass, bottom-up routability-driven routing framework and features a new redundant-via aware detailed maze routing algorithm (which could be applied to both gridless and grid-based routing). We also propose a graph-matching based post-layout double-via insertion algorithm to achieve a higher insertion rate. In particular, the algorithm is optimal for grid-based routing with up to three routing layers and the stacked-via structure. Experiments show that our methods significantly improve the via count, number of dead vias, double-via insertion rates, and running times.