Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
Proceedings of the 37th Annual Design Automation Conference
Introduction to Algorithms
Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Multilevel routing with antenna avoidance
Proceedings of the 2004 international symposium on Physical design
Optical proximity correction (OPC): friendly maze routing
Proceedings of the 41st annual Design Automation Conference
Coupling aware timing optimization and antenna avoidance in layer assignment
Proceedings of the 2005 international symposium on Physical design
Improved multilevel routing with redundant via placement for yield and reliability
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
RADAR: RET-aware detailed routing using fast lithography simulations
Proceedings of the 42nd annual Design Automation Conference
Post-routing redundant via insertion for yield/reliability improvement
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Maze routing with OPC consideration
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Redundant-via enhanced maze routing for yield improvement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A layout dependent full-chip copper electroplating topography model
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Wire density driven global routing for CMP variation and timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Optimal post-routing redundant via insertion
Proceedings of the 2008 international symposium on Physical design
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
Proceedings of the 45th annual Design Automation Conference
Predictive formulae for OPC with applications to lithography-friendly routing
Proceedings of the 45th annual Design Automation Conference
Full-Chip Nanometer Routing Techniques
Full-Chip Nanometer Routing Techniques
A novel wire-density-driven full-chip routing system for CMP variation control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel Full-Chip Routing With Testability and Yield Enhancement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Full-Chip Routing Considering Double-Via Insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
| Hi-index | 0.00 |
As IC process geometries scale down to the nanometer territory, industry faces severe challenges of manufacturing limitations. To guarantee high yield and reliability, routing for manufacturability and reliability has played a pivotal role in resolution and thus yield enhancement for the imperfect manufacturing process. In this article, we introduce major routing challenges arising from nanometer process, survey key existing techniques for handling the challenges, and provide some future research directions in routing for manufacturability and reliability.