A layout dependent full-chip copper electroplating topography model

Authors:
Jianfeng Luo;Qing Su;C. Chiang;J. Kawa
Affiliations:
Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA;Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA;Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA;Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
Venue:
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Year:
2005

Citing 2
Cited 7

Chemical-mechanical polishing of copper for interconnect formation

AMI '96 Proceedings of the symposium J of the 1996 E-MRS Spring meeting conference on Advanced materials for interconnections
Modeling the effects of systematic process variation on circuit performance

Modeling the effects of systematic process variation on circuit performance

DFM issues for 65nm and beyond

Proceedings of the 17th ACM Great Lakes symposium on VLSI
Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Full-chip routing system for reducing Cu CMP & ECP variation

Proceedings of the 21st annual symposium on Integrated circuits and system design
A novel wire-density-driven full-chip routing system for CMP variation control

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routing for manufacturability and reliability

IEEE Circuits and Systems Magazine
ECP- and CMP-aware detailed routing algorithm for DFM

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crosstalk-induced delay, noise, and interconnect planarization implications of fill metal in nanoscale process technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, a layout dependent full-chip electroplating (ECP) topography model is developed based on the additive nature of the physics of the EP process. Two layout attributes: layout density, and feature perimeter sum are used to compute the post-ECP topography. Under a unified mechanism, two output variables representing the final topography: the array height and the step height are modeled simultaneously. Using the proposed model long-range effects of the ECP process can be incorporated easily as well. The simulation results of our model were verified with test structure experimental data published in the literature and are presented in this paper. The results show that the errors are less than 5%. This model is not limited to the regular test structures; it can also be used for any practical design. The results of such partial application are shown here as well. Our proposed ECP model can be used to model systematic variations caused by an ECP process or by a chemical mechanical planarization (CMP) process. The potential applications of this model include: layout design evaluation for catastrophic failure prevention; yield aware design (design for manufacturability), and variation- aware timing analysis.