A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
A layout dependent full-chip copper electroplating topography model
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Fast and efficient phase conflict detection and correction in standard-cell layouts
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
| Hi-index | 0.00 |
The 90nm technology node is a mature process and is currently in full production. It was the first node to challenge the limitations of 193 nm lithography in a significant way. Many creative solutions were devised to circumvent those limitations and a lot was learned in the process. Now 65nm, 45nm, and 32nm are pushing the envelope of every aspect of the design and manufacturing flow; not just lithography but also in device engineering, device modeling, and design methodology. Design for Manufacturability (DFM) and Design for Yield (DFY) dictate that we optimize every step in the design flow. Here we address a plurality of those challenges.