Modeling the effects of systematic process variation on circuit performance

Explicit computation of performance as a function of process variation

Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems

A multiple level network approach for clock skew minimization with process variations

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

A multi-level transmission line network approach for multi-giga hertz clock distribution

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Statistical clock tree routing for robustness to process variations

Proceedings of the 2006 international symposium on Physical design

A layout dependent full-chip copper electroplating topography model

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Yield-Aware Cache Architectures

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture

Variability-tolerant NoC link design

Proceedings of the Fifth International Workshop on Network on Chip Architectures