Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Timing Yield Estimation from Static Timing Analysis
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Modeling the effects of systematic process variation on circuit performance
Modeling the effects of systematic process variation on circuit performance
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical gate delay model considering multiple input switching
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Clock Skew Analysis Considering Intra-Die Process Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Efficient computation of the worst-delay corner
Proceedings of the conference on Design, automation and test in Europe
Path criticality computation in parameterized statistical timing analysis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Testability driven statistical path selection
Proceedings of the 48th Design Automation Conference
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Each manufactured chip is a little bit different, and designers want as many as possible of these chips to work. Process variation is a function of many variables, as the width, thickness, and inter-layer thickness can vary independently for each layer on a chip, as can temperature and voltage. Currently designers cope with this by picking a few subsets of these conditions, called process corners, and analyzing at these conditions. However, it's easy to show this approach is both too conservative (the specified conditions will seldom occur) and not conservative enough (it misses errors that can occur due to process variation). We present a unified theory of process variation that includes inter-chip variation, intra-chip deterministic variation (such as caused by proximity effects and metal density), and intra-chip statistical variation. Using this mechanism, we can explicitly compute performance as a function of process variation. This allows us to compute less pessimistic timing numbers and address yield optimization in the design process.