Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Subwavelength optical lithography: challenges and impact on physical design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Statistical skew modeling for general clock distribution networks in presence of process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical clock skew modeling with data delay variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Explicit computation of performance as a function of process variation
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Worst case clock skew under power supply variations
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Process variation aware clock tree routing
Proceedings of the 2003 international symposium on Physical design
Impact Analysis of Process Variability on Clock Skew
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Process-induced skew reduction in nominal zero-skew clock trees
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Delay Fault Diagnosis for Non-Robust Test
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
Clock tree synthesis with data-path sensitivity matching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Tolerating process variations in high-level synthesis using transparent latches
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With shrinking cycle times, clock skew has become an increasinglydifficult and important problem for high performance designs.Traditionally, clock skew has been analyzed using case-files whichcannot model intra-die process variations and hence result in a veryoptimistic skew analysis. In this paper, we present a statistical skewanalysis method to model intra-die process variations. We firstpresent a formal model of the statistical clock skew problem and thenpropose an algorithm which is based on propagation of joint probabilitydistribution functions in a bottom up fashion in a clock tree.The analysis accounts for topological correlations between pathdelays and has linear run time with the size of the clock tree. Theproposed method was tested on several large clock tree circuits,including a clock tree from a large industrial high-performancemicroprocessor. The results are compared with Monte Carlo simulationfor accuracy comparison and demonstrate the need for statisticalanalysis of clock skew.