Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Full-chip verification methods for DSM power distribution systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
Model and analysis for combined package and on-chip power grid simulation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
Coping with buffer delay change due to power and ground noise
Proceedings of the 39th annual Design Automation Conference
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Timing analysis including clock skew
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clock skew verification in the presence of IR-drop in the power distribution network
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clock network sizing via sequential linear programming with time-domain analysis
Proceedings of the 2004 international symposium on Physical design
Statistical Clock Skew Analysis Considering Intra-Die Process Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Clock skew bounds estimation under power supply and process variations
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
| Hi-index | 0.00 |
On-chip power distribution networks are resistive in nature and hence create large variations in the voltage levels across the chip. These variations have significant impact on the delays of global signals, such as the clock, which span the entire chip. A clock network that is balanced without considering delay variations induced by power supply variations can suffer significant degradation of its skew during the chips operation. In this paper, we describe a practical approach to determining the worst-case skew in a clock network in the presence of power supply variations. Experiments using the proposed approach on the clock nets of several processors show that clock skew can nearly double in the worst case. The proposed methodology is easily extendable for studying the impact of process variations and on-chip parasitic inductance on clock skew.