Effects of simultaneous switching noise on the tapered buffer design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CMOS gate delay models for general RLC loading
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Analysis and Optimization of Ground Bounce in Digital CMOS Circuits
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Buffer insertion for noise and delay optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clock skew verification in the presence of IR-drop in the power distribution network
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst case clock skew under power supply variations
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
A practical CAD technique for reducing power/ground noise in DSM circuits
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Analysis and Optimization of Power Grids
IEEE Design & Test
Clock and Power Gating with Timing Closure
IEEE Design & Test
Buffer delay change in the presence of power and ground noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Vectorless Analysis of Supply Noise Induced Delay Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Low-power on-chip communication based on transition-aware global signaling (TAGS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing analysis considering spatial power/ground level variation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing analysis considering temporal supply voltage fluctuation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Static timing analysis considering power supply variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Enhancing beneficial jitter using phase-shifted clock distribution
Proceedings of the 13th international symposium on Low power electronics and design
Timing Analysis Considering Spatial Power/Ground Level Variation
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Timing Analysis Considering Temporal Supply Voltage Fluctuation
IEICE - Transactions on Information and Systems
Synthesis of low power clock trees for handling power-supply variations
Proceedings of the 2011 international symposium on Physical design
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Variation of power and ground levels affect VLSI circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise on signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply level-induced jitter characteristics.