Gate-level current waveform simulation of CMOS integrated circuits
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Clock Skew Optimization for Peak Current Reduction
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Coping with buffer delay change due to power and ground noise
Proceedings of the 39th annual Design Automation Conference
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Power Supply Noise Suppression via Clock Skew Scheduling
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
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One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In this work we propose a CAD optimization technique to spread out the switching times of different gates in a circuit to reduce its SSN, by sizing them appropriately. We make sure that its critical delay does not increase while its p/g noise decreases. Our formulation is a Linear Programming one, which we have efficiently formulated and solved. On average, improvements of 28% in the maximum peak-peak voltage fluctuations in the power networks, and that of 20% in the ground networks were achieved by our method over the original circuit implementations. These results were obtained without any performance penalty. As a positive effect of gate-sizing, the power dissipation in the optimized circuits, on average, was reduced to about half of the unoptimized ones for the same supply voltage. We have used standard commercial design flows for all our experiments, and all the results have been validated by extensive SPICE simulations.