A practical CAD technique for reducing power/ground noise in DSM circuits
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Vector extraction for average total power estimation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Input-specific dynamic power optimization for VLSI circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Variable input delay CMOS logic for low power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of variable input delay gates for low dynamic power circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized when every gate has no more than one output transition per clock cycle. This condition is achieved for a gate when the gate delay equals or exceeds the maximum difference between path delays at gate inputs. In practice, path delays are adjusted either by increasing gate delays or by inserting delay buffers. The minimum transient energy design is obtained when no delay buffer is added. This design requires possible increases in gate delays to meet the minimum energy condition at all gates. However, the delay of the critical path may be increased. In an alternative design, where the critical path delay is not allowed to increase, delay buffers may have to be added. The theory in this paper allows trade-offs between minimum transient energy and critical path delay. We formulate the problem as a linear program to obtain the minimum transient energy design with the smallest number of delay buffers for a given overall delay of the circuit. An optimized four-bit ALU circuit is found to consume 53% peak and 73% average power compared to the original circuit.