A practical CAD technique for reducing power/ground noise in DSM circuits
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Improved algorithms for link-based non-tree clock networks for skew variability reduction
Proceedings of the 2005 international symposium on Physical design
Register placement for low power clock network
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Variation tolerant buffered clock network synthesis with cross links
Proceedings of the 2006 international symposium on Physical design
Associative skew clock routing for difficult instances
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock buffer polarity assignment for power noise reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient merging scheme for prescribed skew clock routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reconfigurable clock polarity assignment flow for clock gated designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Simultaneous switching events in the clock lines and the signals passing through sequential and combinational logic elements cause large L di/dt and IR voltage variations in the power and ground network. This is known as power supply noise and it affects the performance and reliability of the entire circuit. In this paper, we propose an algorithm that performs clock skew scheduling to minimize the number of simultaneous switching events such that the power supply noise is suppressed. Our approach establishes a direct relationship between current (drawn by a circuit element, sequential or combinational) and skew by the concept of envelope waveforms, using a graphical representation. We provide a graph-based scheduling approach to reduce the peak current and to minimize the difference between the current peaks and valleys so that the current profile of the entire circuit is smoothened. Our approach also guarantees that the resulting clock schedule does not violate setup and hold time constraints. Experimental results on benchmark circuits show an average reduction of 19.6% in the peak current, an average reduction of 38.7% in the current swing, and an average reduction of 47.4% in voltage variations in the power lines using our approach.