Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs

Authors:
Tsung-Yi Wu;Tzi-Wei Kao;Shi-Yi Huang;Tai-Lun Li;How-Rern Lin
Affiliations:
National Changhua University of Education, Taiwan;National Changhua University of Education, Taiwan;National Changhua University of Education, Taiwan;National Changhua University of Education, Taiwan;Providence University, Taiwan
Venue:
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Year:
2010

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Abstract

In a typical synchronous SoC design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.