Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock Skew Optimization for Peak Current Reduction
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Decoupling capacitance allocation for power supply noise suppression
Proceedings of the 2001 international symposium on Physical design
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
Introduction to Algorithms
Analysis and Optimization of Power Grids
IEEE Design & Test
Power Supply Noise Suppression via Clock Skew Scheduling
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Buffer delay change in the presence of power and ground noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Minimizing peak current via opposite-phase clock tree
Proceedings of the 42nd annual Design Automation Conference
Skew scheduling and clock routing for improved tolerance to process variations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Practical techniques to reduce skew and its variations in buffered clock networks
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Skew spreading for peak current reduction
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Clock skew verification in the presence of IR-drop in the power distribution network
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
General skew constrained clock network sizing based on sequential linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: 1) partitioning; 2) 2-coloring on minimum spanning tree; and 3) recursive minmatching. A post-processing of clock buffer sizing is performed to achieve desired clock skew. SPICE based experimental results indicate that our techniques could reduce the average peak current and average delay variations by 50% and 51%, respectively.