Clock buffer polarity assignment for power noise reduction
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Discrete buffer and wire sizing for link-based non-tree clock networks
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 2009 International Conference on Computer-Aided Design
Accurate clock mesh sizing via sequential quadraticprogramming
Proceedings of the 19th international symposium on Physical design
Clock skew optimization considering complicated power modes
Proceedings of the Conference on Design, Automation and Test in Europe
Discrete buffer and wire sizing for link-based non-tree clock networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Buffered clock tree sizing for skew minimization under power and thermal budgets
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock skew minimization in multi-voltage mode designs using adjustable delay buffers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Clock buffer polarity assignment for power noise reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2013 ACM international symposium on International symposium on physical design
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem
Proceedings of the 50th Annual Design Automation Conference
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We investigate the problem of clock network sizing subject to general skew constraints. A novel approach based on sequential linear programming is presented. The original nonlinear programming problem is transformed into a sequence of linear programs by taking the first-order Taylor's expansion of clock path delay with respect to buffer and/or wire widths. For each linear program, the sensitivities of clock path delay, with respect to buffer and/or wire widths, are efficiently updated by applying time-domain analysis to the clock network in a divide-and-conquer fashion. Our technique can take into account power supply and process variations. We demonstrate experimentally that the proposed technique is not only capable of optimizing effectively the skew and area of clock network, but also of providing more accurate delay and skew results compared to the traditional approaches.