Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Making large-scale support vector machine learning practical
Advances in kernel methods
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
Proceedings of the 2003 international symposium on Physical design
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Improved algorithms for link-based non-tree clock networks for skew variability reduction
Proceedings of the 2005 international symposium on Physical design
Variation tolerant buffered clock network synthesis with cross links
Proceedings of the 2006 international symposium on Physical design
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical based link insertion for robust clock network design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Practical techniques to reduce skew and its variations in buffered clock networks
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
General skew constrained clock network sizing based on sequential linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate clock mesh sizing via sequential quadraticprogramming
Proceedings of the 19th international symposium on Physical design
On-chip em-sensitive interconnect structures
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
| Hi-index | 0.00 |
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's attention due to its appealing tradeoff between variation tolerance and power overhead. In this work, we investigate how to optimize such clock networks through buffer and wire sizing. A two-stage hybrid optimization approach is proposed. It considers the realistic constraint of discrete buffer/wire sizes and is based on accurate delay models. In order to provide reliable and efficient guidance for the optimization, we suggest to apply SVM (Support Vector Machine) based machine learning as a surrogate for expensive circuit-level simulation. Experimental results on benchmark circuits show that our sizing method can reduce clock skew by 43% on average with very small increase on power dissipation