On-chip em-sensitive interconnect structures

Authors:
Di-an Li;Malgorzata Marek-Sadowska;Bill Lee
Affiliations:
University of California, Santa Barbara, Goleta, CA, USA;University of California, Santa Barbara, Goleta, CA, USA;Lam Research Corporation, Fremont, CA, USA
Venue:
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Year:
2010

Citing 8
Cited 0

Coupled analysis of electromigration reliability and performance in ULSI signal nets

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Clock Distribution Architectures: A Comparative Study

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Practical techniques to reduce skew and its variations in buffered clock networks

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design tools for reliability analysis

Proceedings of the 43rd annual Design Automation Conference
Discrete buffer and wire sizing for link-based non-tree clock networks

Proceedings of the 2008 international symposium on Physical design
iTEM: a temperature-dependent electromigration reliability diagnosis tool

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Static electromigration analysis for on-chip signal interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Due to ever greater current densities in modern IC designs, electromigration (EM) in copper interconnects has become an important reliability factor. In this paper, we analyze current densities on bus and clock networks. We observe that under certain conditions, these networks may become sensitive to EM effects and prone to failure. We perform SPICE simulations on open source Wishbone bus and non-tree clocks for IBM and ISCAS89 benchmarks. Experiments on these networks show that on some wire segments current may flow predominantly in one direction and its density may exceed the maximum allowed values suggested by the International Technology Roadmap for Semiconductors (ITRS). When power network experiences noise, the links of a non-tree clock may carry currents whose densities could be 100 times greater than those of the tree branches. In our study, we compare various methods of reducing the EM effect on interconnects. We demonstrate that in comparison to such design methods as increasing wire widths, reducing circuit frequency or decreasing driver sizes, the technology-based solution of capping copper (Cu) wires with cobalt tungsten phosphide (CoWP) coating works best and eliminates EM violations without area overhead, performance loss or additional design effort.