Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation
Proceedings of the 2007 international symposium on Physical design
Unified adaptivity optimization of clock and logic signals
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2009 International Conference on Computer-Aided Design
An efficient and optimal algorithm for simultaneous buffer and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
General skew constrained clock network sizing based on sequential linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem
Proceedings of the 50th Annual Design Automation Conference
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Satisfying clock skew constraint is one of the most important tasks in the clock tree synthesis. Moreover, the task becomes much harder to solve as the clock tree is designed under multiple power mode environment, in which the voltage applied to some design module varies as the power mode changes. Recently, it is shown that adjustable delay buffer (ADB) whose delay can be tuned dynamically can be used to solve the clock skew problem effectively under multiple power modes. However, due to the area/control overhead by ADBs it is very important to minimize the number of ADBs. This work provides a complete solution to the problem of clock skew minimization using ADBs under multiple power modes. We propose a linear-time optimal algorithm that simultaneously solves the problems of computing (1) the minimum number of ADBs to be used, (2) the location at which each ADB is to be placed, and (3) the delay value of each ADB to be assigned to each power mode. Experimental results show that in comparison with the previous work [8] which iteratively performs the ADB allocation, placement, and delay assignment, our integrated algorithm produces consistently better designs for all tested benchmarks under four power modes, reducing the number of ADBs by 9.27% further on average at skew bound of 30ps~50ps even with shorter clock latencies.