A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Dynamic thermal clock skew compensation using tunable delay buffers
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the 2009 International Conference on Computer-Aided Design
Clock skew minimization in multi-voltage mode designs using adjustable delay buffers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
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It is well known that clock skew minimization becomes critical in high-performance VLSI designs. In this paper, the assignment of adjustable delay buffers(ADBs) is applied to minimize the clock skew in a buffered clock tree in a multi-voltage mode design. Given a buffered clock tree, based on the assignment flexibility of the delay value on an ADB, bottom-up ADB assignment is firstly proposed to insert ADBs to minimize the clock skew by assigning the delay values of the inserted ADBs for each power mode. Furthermore, bottom-up ADB elimination is proposed to eliminate the redundant ADBs to minimize the number of the inserted ADBs in a multi-voltage mode design while maintaining the minimized clock skew. Compared with Su's heuristic algorithm and Lim's optimal algorithm, the experimental results show that our proposed algorithm uses less CPU time to reduces 9.3% of the used ADBs and 1.3%~1.6% of the average latency on the average, respectively.