Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A novel clock distribution and dynamic de-skewing methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation
Proceedings of the 2007 international symposium on Physical design
Unified adaptivity optimization of clock and logic signals
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2009 International Conference on Computer-Aided Design
Clock skew minimization in multi-voltage mode designs using adjustable delay buffers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Clock Tree synthesis for TSV-based 3D IC designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An efficient and optimal algorithm for simultaneous buffer and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
General skew constrained clock network sizing based on sequential linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Meeting clock skew constraint is one of the most important tasks in the synthesis of clock trees. Moreover, the problem becomes much hard to tackle as the delay of clock signals varies dynamically during execution. Recently, it is shown that adjustable delay buffer (ADB) whose delay can be adjusted dynamically can solve the clock skew variation problem effectively. However, inserting ADBs requires non-negligible area and control overhead. Thus, all previous works have invariably aimed at minimizing the number of ADBs to be inserted, particularly under the environment of multiple power modes in which the operating voltage applied to some modules varies as the power mode changes. In this work, unlike the previous works which have solved the ADB minimization problem heuristically or locally optimally, we propose an elegant and easily adoptable solution to overcome the limitation of the previous works. Precisely, we propose an O(n log n) time (bottom-up traversal) algorithm that (1) optimally solves the problem of minimizing the number of ADBs to be inserted with continuous delay of ADBs and (2) enables solving the ADB insertion problem with discrete delay of ADBs to be greatly simple and predictable. In addition, we propose (3) a systematic solution to an important extension to the problem of buffer sizing combined with the ADB insertion to further reduce the ADBs to be used.