Simultaneous buffer and wire sizing for performance and power optimization

An efficient approach to simultaneous transistor and interconnect sizing

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Interconnect design for deep submicron ICs

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

A new approach to simultaneous buffer insertion and wire sizing

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Global interconnect sizing and spacing with consideration of coupling capacitance

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Closed form solution to simultaneous buffer insertion/sizing and wire sizing

Proceedings of the 1997 international symposium on Physical design

Greedy wire-sizing is linear time

ISPD '98 Proceedings of the 1998 international symposium on Physical design

LIBRA—a library-independent framework for post-layout performance optimization

ISPD '98 Proceedings of the 1998 international symposium on Physical design

Bounded-skew clock and Steiner routing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A polynomial time optimal algorithm for simultaneous buffer and wire sizing

Proceedings of the conference on Design, automation and test in Europe

Closed form solutions to simultaneous buffer insertion/sizing and wire sizing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

Proceedings of the 2002 international symposium on Physical design

Clock-tree power optimization based on RTL clock-gating

Proceedings of the 40th annual Design Automation Conference

Buffer Library Selection

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Power-aware clock tree planning

Proceedings of the 2004 international symposium on Physical design

Closing the power gap between ASIC and custom: an ASIC perspective

Proceedings of the 42nd annual Design Automation Conference

Power-aware placement

Proceedings of the 42nd annual Design Automation Conference

Design and verification of high-speed VLSI physical design

Journal of Computer Science and Technology

On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect

Self-heating-aware optimal wire sizing under Elmore delay model

Proceedings of the conference on Design, automation and test in Europe

Value assignment of Adjustable Delay Buffers for clock skew minimization in multi-voltage mode designs

Proceedings of the 2009 International Conference on Computer-Aided Design

Interconnect power and delay optimization by dynamic programming in gridded design rules

Proceedings of the 19th international symposium on Physical design

A power-efficient multipin ILP-based routing technique

IEEE Transactions on Circuits and Systems Part I: Regular Papers

An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs

Proceedings of the 16th Asia and South Pacific Design Automation Conference

POMR: a power-aware interconnect optimization methodology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A study on factors influencing power consumption in multithreaded and multicore CPUs

WSEAS Transactions on Computers

Reducing expected delay and power in FPGAs using buffer insertion in single-driver wires

Microelectronics Journal

An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem

Proceedings of the 50th Annual Design Automation Conference