Simultaneous gate and interconnect sizing for circuit-level delay optimization

Authors:
Noel Menezes;Satyamurthy Pullela;Lawrence T. Pileggi
Affiliations:
Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX;Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX;Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
Venue:
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Year:
1995

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