A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Simultaneous gate and interconnect sizing for circuit-level delay optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Technology mapping for high-performance static CMOS and pass transistor logic designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
Addressing library creation challenges from recent Liberty extensions
Proceedings of the 45th annual Design Automation Conference
Current source modeling in the presence of body bias
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
BDD decomposition for delay oriented pass transistor logic synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Delay model for reconfigurable logic gates based on graphene PN-junctions
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Compact current source models for timing analysis under temperature and body bias variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transistor-level gate model based statistical timing analysis considering correlations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Cell characterization data is used by synthesis and timing verificationtools to compile and validate a cell netlist which meets timingconstraints imposed by the designer. Characterization tablescontain data for multiple, simple equations representing a cell's behaviorand are an alternative to the single, monolithic characteristicequation. Data in the table is fit to a function whose form isfixed by the application, and the cellýs response is interpolated fromthe function. Tables can potentially increase accuracy, but large tablescan cause a program to use dramatically more memory and runmuch slower. The optimization of characterization tables, in whichaccuracy is maintained but table size is significantly reduced, is importantif large programs, such as synthesis, are to complete accuratelyand in a reasonable runtime. In this paper we address someof the issues involved in characterizing cells and optimizing characterizationtables quickly and accurately. Experimental results fromthe use of these techniques within AMD for a Synopsys cell libraryis also presented.