DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Introduction to algorithms
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A near optimal algorithm for technology mapping minimizing area under delay constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A fast and accurate technique to optimize characterization tables for logic synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Library-less synthesis for static CMOS combinational logic circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
SOCRATES: a system for automatically synthesizing and optimizing combinational logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
BDD Decomposition for Efficient Logic Synthesis
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Technology mapping using boolean matching and don't care sets
EURO-DAC '90 Proceedings of the conference on European design automation
C5M-a control-logic layout synthesis system for high-performance microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Exact lower bound for the number of switches in series to implement a combinational logic cell
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
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Two new techniques for mapping circuits are proposed in this paper. The first method, called the odd-level transistor replacement (OTR) method, has a goal that is similar to that of technology mapping, but without the restriction of a fixed library size and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the static CMOS/pass transistor logic (PTL) method, uses a mix of static CMOS and PTL to realize the circuit and utilized the relation between PTL and binary decision diagrams. The methods are very efficient and can handle all of the ISCAS'85 benchmark circuits in minutes. A comparison of the results with traditional technology mapping using SIS on different libraries shows an average delay reduction above 18% for OTR, and an average delay reduction above 35% for the static CMOS/PTL method, with significant savings in the area