Exact lower bound for the number of switches in series to implement a combinational logic cell

Authors:
F. R. Schneider;R. P. Ribas;S. S. Sapatnekar;A. I. Reis
Affiliations:
Instituto de Informática - UFRGS CEP - Caixa Postal Porto Alegre - RS - Brasil;Instituto de Informática - UFRGS CEP - Caixa Postal Porto Alegre - RS - Brasil;Department of Electrical and Computer Engineering 200 Union Street SE, University of Minnesota, MN;Department of Electrical and Computer Engineering 200 Union Street SE, University of Minnesota, MN
Venue:
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Year:
2005

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Abstract

This paper addresses the question of how many serial switches are necessary to implement a given logic function as a switch network. This issue is important because it affects directly the resistance that will be charging/discharging output loads, thus affecting cell and circuit performance. We derive exact lower bounds to easily evaluate the number of serial switches needed and demonstrate that Complementary Series/Parallel (CSP) and Pass Transistor Logic (PTL) topologies exceed the lower bounds for many practical examples. We also propose a design methodology that will produce cells with minimum number of transistors in series and evaluate the benefits obtained in circuit delay.