Area impact analysis of via-configurable regular fabric for digital integrated circuit design

Authors:
Vinícius Dal Bem;Paulo F. Butzen;Carlos E. Klock;Vinicius Callegaro;André I. Reis;Renato P. Ribas
Affiliations:
Federal University of Rio Grande do Sul, Porto Alegre, Brazil;Federal University of Rio Grande do Sul & Federal University of Rio Grande, Porto Alegre & Rio Grande, Brazil;Federal University of Rio Grande do Sul, Porto Alegre, Brazil;Federal University of Rio Grande do Sul, Porto Alegre, Brazil;Federal University of Rio Grande do Sul, Porto Alegre, Brazil;Federal University of Rio Grande do Sul, Porto Alegre, Brazil
Venue:
Proceedings of the 24th symposium on Integrated circuits and systems design
Year:
2011

Citing 16
Cited 0

Combinatorial optimization: algorithms and complexity

Combinatorial optimization: algorithms and complexity
CELLERITY: a fully automatic layout synthesis system for standard cell libraries

DAC '97 Proceedings of the 34th annual Design Automation Conference
Switching Theory for Logic Synthesis

Switching Theory for Logic Synthesis
Synthesis and placement flow for gain-based programmable regular fabrics

Proceedings of the 2003 international symposium on Physical design
Structured ASICs: Opportunities and Challenges

ICCD '03 Proceedings of the 21st International Conference on Computer Design
Exploring Logic Block Granularity for Regular Fabrics

Proceedings of the conference on Design, automation and test in Europe - Volume 1
Design automation for mask programmable fabrics

Proceedings of the 41st annual Design Automation Conference
Design methodology for IC manufacturability based on regular logic-bricks

Proceedings of the 42nd annual Design Automation Conference
Exact lower bound for the number of switches in series to implement a combinational logic cell

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A metal and via maskset programmable VLSI design methodology using PLAs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimal Layout of CMOS Functional Arrays

IEEE Transactions on Computers
Standard Cell Like Via-Configurable Logic Block for Structured ASICs

ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Switch level optimization of digital CMOS gate networks

ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Co-optimization of circuits, layout and lithography for predictive technology scaling beyond gratings

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Designing via-configurable logic blocks for regular fabric

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PLA-based regular structures and their synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Transistor regular layout (TRL) has been considered a more lithography-reliable approach for digital integrated circuit design than the most conventional standard cell design. However, the impact in circuit area seems to be unavoidable due to the loss in design flexibility. Hence, the decision in applying such design strategy depends not only on the expected yield improvement but also on the careful evaluation of circuit penalty. This paper presents an extensive analysis and discussion about area impact of TRL design style in comparison to the standard cell one. Several benchmark circuits were mapped by addressing specific cell libraries built for this purpose. Experimental results demonstrated that efficient TRL templates may minimize significantly the area overhead.