Automatic layout of low-cost quick-turnaround random-logic custom LSI devices
DAC '76 Proceedings of the 13th Design Automation Conference
LTX - a system for the directed automatic design of LSI circuits
DAC '76 Proceedings of the 13th Design Automation Conference
SLIC - Symbolic Layout of Integrated Circuits
DAC '76 Proceedings of the 13th Design Automation Conference
Optimal layout of CMOS functional arrays
Optimal layout of CMOS functional arrays
A study of current logic design problems: part i, design of diagnosable mos networks; part ii, minimum nor (nand) networks for parity functions of an arbitrary number of variables; part iii, minimum parallel binary adders with nor (nand) gates and their extensions to networks consisting of carry-save adders.
Minimal Negative Gate Networks
IEEE Transactions on Computers
Synthesis of Networks with a Minimum Number of Negative Gates
IEEE Transactions on Computers
Computer-Aided Preliminary Layout Design of Customized MOS Arrays
IEEE Transactions on Computers
Layout synthesis of MOS digital cells
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Transistor Level Synthesis Dedicated to Fast I.P. Prototyping
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
HAL: heuristic algorithms for layout synthesis
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Finding Double Euler Trails of Planar Graphs in Linear Time
FOCS '99 Proceedings of the 40th Annual Symposium on Foundations of Computer Science
Optimal layout of CMOS functional arrays
DAC '79 Proceedings of the 16th Design Automation Conference
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Exact combinatorial optimization methods for physical design of regular logic bricks
Proceedings of the 44th annual Design Automation Conference
A comparative study of CMOS gates with minimum transistor stacks
Proceedings of the 20th annual conference on Integrated circuits and systems design
Transistor-level layout of high-density regular circuits
Proceedings of the 2009 international symposium on Physical design
An automatic cell pattern generation system for CMOS transistor-pair array LSI
Integration, the VLSI Journal
Performance study of VeSFET-based, high-density regular circuits
Proceedings of the 19th international symposium on Physical design
Layout generator for transistor-level high-density regular circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Area impact analysis of via-configurable regular fabric for digital integrated circuit design
Proceedings of the 24th symposium on Integrated circuits and systems design
Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the Conference on Design, Automation and Test in Europe
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Designers of MOS LSI circuits can take advantage of complex functional cells in order to achieve better performance. This paper discusses the implementation of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented. This method is useful for the design of cells used in conventional design automation systems.