Layout optimization of CMOS functional cells
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Dual Eulerian Properties of Plane Multigraphs
SIAM Journal on Discrete Mathematics
SIAM Journal on Computing
The recognition of double Euler trails in series-parallel networks
Journal of Algorithms
Optimal Layout of CMOS Functional Arrays
IEEE Transactions on Computers
Euler paths in series parallel graphs
STOC '01 Proceedings of the thirty-third annual ACM symposium on Theory of computing
The SPQR-tree data structure in graph drawing
ICALP'03 Proceedings of the 30th international conference on Automata, languages and programming
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This paper answers an open question in the design of complimentary metal-oxide semiconductor (CMOS) VLSI circuits. It asks whether a polynomial-time algorithm can decide if a given planar graph has a plane embedding E such that E has an Euler trail \math and its dual graph has an Euler trail \math, where \math is the dual edge of \math for \math. This paper answers this question in the affirmative, by presenting a linear-time algorithm.