The layout synthesizer: an automatic Netlist-to-Layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
GENAC: an automatic cell synthesis tool
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Exact width and height minimization of CMOS cells
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Euler paths in series parallel graphs
STOC '01 Proceedings of the thirty-third annual ACM symposium on Theory of computing
Finding Double Euler Trails of Planar Graphs in Linear Time
FOCS '99 Proceedings of the 40th Annual Symposium on Foundations of Computer Science
Transistor placement and interconnect algorithms for leaf cell synthesis
EURO-DAC '90 Proceedings of the conference on European design automation
Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs
Proceedings of the conference on Design, automation and test in Europe
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An optimal non-exhaustive method of minimizing the layout area of complementary series-parallel CMOS functional cells in the standard-cell style is presented. This generalizes earlier work of Uehara and van Cleemput which is heuristic and nonoptimal. A complete graph-theoretical framework for CMOS cell layout is developed and illustrated. The approach demonstrates a new class of graph-based algebras which characterize this layout problem.