Aesop: a tool for automated transistor sizing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Layout optimization of CMOS functional cells
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
The layout synthesizer: an automatic Netlist-to-Layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
GENAC: an automatic cell synthesis tool
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A high packing density module generator for CMOS logic cells
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
SOLO: a generator of efficient layouts from optimized MOS circuit schematics
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
An efficient layout style for 2-metal CMOS leaf cells and their automatic generation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Exact width and height minimization of CMOS cells
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An efficient transistor folding algorithm for row-based CMOS layout design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design Synthesis and Silicon Compilation
IEEE Design & Test
HAL: heuristic algorithms for layout synthesis
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
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We present an automatic layout generation system, called LiB, for the library cells used in CMOS ASIC design. LiB takes a transistor-level circuit schematic in SPICE format and outputs a symbolic layout. Our layout style is similar to that proposed by Uehara and van Cleemput in [17]. We propose several heuristic algorithms to solve the transistor-clustering, -pairing, -chaining, -folding, the chain placement, the routing, and the net assignment problems, respectively. Experimental results are presented to show the capability of LiB.