Layout optimization of CMOS functional cells
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
FLOSS: an approach to automated layout for high-volume designs
25 years of DAC Papers on Twenty-five years of electronic design automation
A high packing density module generator for CMOS logic cells
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
SOLO: a generator of efficient layouts from optimized MOS circuit schematics
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Layout synthesis of MOS digital cells
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An efficient layout style for 2-metal CMOS leaf cells and their automatic generation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Routing considerations in symbolic layout synthesis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Automatic layout synthesis of leaf cells
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Width minimization of two-dimensional CMOS cells using integer programming
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
CELLERITY: a fully automatic layout synthesis system for standard cell libraries
DAC '97 Proceedings of the 34th annual Design Automation Conference
The future of custom cell generation in physical synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Optimal 2-D cell layout with integrated transistor folding
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A cell synthesis method for salicide process
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
HAL: heuristic algorithms for layout synthesis
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
XPRESS: A Cell Layout Generator with Integrated Transistor Folding
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Reducing Library Development Cycle Time through an Optimum Layout Create Flow
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
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A system generating compacted physical layouts from MOS transistor netlists has been developed. It uses a novel graph-theoretical placement algorithm to simultaneously maximize diffusion sharing and minimize the wiring area. The algorithm is not limited to circuits that have equal numbers of NMOS and PMOS transistors. A special-purpose router using either one-layer or two-layer metal is described. Experimental results for area efficiency and run-time performance are very promising.