XPRESS: A Cell Layout Generator with Integrated Transistor Folding

Authors:
Avaneendra Gupta;Siang-Chun The;John P. Hayes
Affiliations:
Design Technology Division, Intel Corporation, 2200 Mission College, Blvd., Santa Clara, CA and Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI;Design Technology Division, Intel Corporation, 2200 Mission College, Blvd., Santa Clara, CA;Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

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Abstract

We describe a method for generating area-efficient layouts of complex CMOS cells in the one-dimensional (linear) style. Its key features are the support for unrestricted circuit structures, transistor sizing via a novel folding technique that integrates folding into the synthesis algorithms, and optimal diffusion sharing. The method has been implemented in the XPRESS cell synthesis tool at Intel Corp. where it is in active use to lay out datapath cells for microprocessors.