Optimal 2-D cell layout with integrated transistor folding

  • Authors:
  • Avaneendra Gupta;John P. Hayes

  • Affiliations:
  • Cadence Design Systems, Inc., 555 River Oaks ParMay, 1A1, San Jose, CA;Dept. of EECS, University of Michigan, 1301 Beal Avenue, Ann Arbor, MI

  • Venue:
  • Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
  • Year:
  • 1998

Quantified Score

Hi-index 0.00

Visualization

Abstract