Integer and combinatorial optimization
Integer and combinatorial optimization
The layout synthesizer: an automatic Netlist-to-Layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
GENAC: an automatic cell synthesis tool
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Transistor chaining and transistor reordering in the design of CMOS complex gates
Transistor chaining and transistor reordering in the design of CMOS complex gates
SOLO: a generator of efficient layouts from optimized MOS circuit schematics
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
XPRESS: A Cell Layout Generator with Integrated Transistor Folding
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Optimum CMOS stack generation with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CLIP: an optimizing layout generator for two-dimensional CMOS cells
DAC '97 Proceedings of the 34th annual Design Automation Conference
C5M—a control logic layout synthesis system for high-performance microprocessors
Proceedings of the 1997 international symposium on Physical design
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Layout generation of array cell for NMOS 4-phase dynamic logic (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Exact minimum-width transistor placement without dual constraint for CMOS cells
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
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We address the problem of CMOS cell width minimization in the general two-dimensional (2-D) layout style and propose a novel technique based on integer linear programming (ILP) to solve it exactly. We formulate a 0-1 ILP model whose solution minimizes cell width along with the routing complexity across the diffusion rows. We present experimental results that evaluate the performance of two ILP solvers that have very different solution methods, and assess the effect of the number of rows on cell width. Run-times for optimal layouts are in seconds for cells with up to 20 transistors. For larger cells, we propose a practical circuit pre-processing scheme that dramatically reduces the run time with little or no loss in optimality.