Layout generation of array cell for NMOS 4-phase dynamic logic (short paper)

• Authors:

• Makoto Furuie;Bao-Yu Song;Yukihiro Yoshida;Takao Onoye;Isao Shirakawa

• Affiliations:

• Dept. of Information Systems Engineering, Osaka University, Suita, Osaka, 565-0871, Japan;Dept. of Information Systems Engineering, Osaka University, Suita, Osaka, 565-0871, Japan;Dept. of Information Systems Engineering, Osaka University, Suita, Osaka, 565-0871, Japan;Dept. of Communications and Computer Engineering, Kyoto University, Kyoto, Kyoto, 606-8501, Japan;Dept. of Information Systems Engineering, Osaka University, Suita, Osaka, 565-0871, Japan

• Venue:
• ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
• Year:
• 2000