Exact width and height minimization of CMOS cells
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Width minimization of two-dimensional CMOS cells using integer programming
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
CELLERITY: a fully automatic layout synthesis system for standard cell libraries
DAC '97 Proceedings of the 34th annual Design Automation Conference
CLIP: an optimizing layout generator for two-dimensional CMOS cells
DAC '97 Proceedings of the 34th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Exact minimum-width transistor placement without dual constraint for CMOS cells
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Exact combinatorial optimization methods for physical design of regular logic bricks
Proceedings of the 44th annual Design Automation Conference
Standard cell routing via boolean satisfiability
Proceedings of the 49th Annual Design Automation Conference
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This paper proposes a cell layout synthesis method via Boolean Satisfiability (SAT). Cell layout synthesis problems are first transformed into SAT problems by our formulations. Our method realizes the high-speed layout synthesis for CMOS logic cells and guarantees to generate the minimum width cells with routability under our layout styles. It considers complementary P-/N-MOSFETs individually during transistor placement, and can generate smaller width layout compared with pairing the complementary P-/N-MOSFETs case. To demonstrate the effectiveness of our SAT-based cell synthesis, we present experimental results which compare it with the 0-1 ILP-based transistor placement method and the commercial cell generation tool. The experimental results show that our SAT-based method can generate minimum width placements in much shorter run time than the 0-1 ILP-based transistor placement method, and can generate the cell layouts of 32 static dual CMOS logic cirsuits in 54% run time with only 3% area increase compared with the commercial tool.