A high packing density module generator for CMOS logic cells

Authors:
Yoichi Shiraishi;Jun'ya Sakemi;Makoto Kutsuwada;Akira Tsukizoe;Takashi Satoh
Affiliations:
Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo, 185, Japan;Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo, 185, Japan;Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo, 185, Japan;Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo, 185, Japan;Device Development Center, Hitachi Ltd., Ome-shi, Tokyo, 198, Japan
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

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Abstract

This paper presents new algorithms for cell pattern generation. The evaluated cell areas are based on measurements which are independent of production process technology. The placement algorithm recognizes logic gates from an unconstrained CMOS circuit diagram and places them in a pattern which minimizes the total wiring length. The generated cell pattern has bent gates and is grid-free. This generator has been applied to more than 60 cell designs used for industrial chips without the need of manual intervention.