An optimum channel-routing algorithm for polycell layouts of integrated circuits
DAC '73 Proceedings of the 10th Design Automation Workshop
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
A high quality, low cost router for MOS/LSI
DAC '72 Proceedings of the 9th Design Automation Workshop
25 years of DAC Papers on Twenty-five years of electronic design automation
A high packing density module generator for CMOS logic cells
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic placement algorithms for high packing density V L S I
DAC '83 Proceedings of the 20th Design Automation Conference
Design automation status in Japan
DAC '81 Proceedings of the 18th Design Automation Conference
A dogleg “optimal” channel router with completion enhancements
DAC '81 Proceedings of the 18th Design Automation Conference
MILD - A cell-based layout system for MOS-LSI
DAC '81 Proceedings of the 18th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
A logic partitioning procedure by interchanging clusters
DAC '75 Proceedings of the 12th Design Automation Conference
On routing for custom integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI
DAC '79 Proceedings of the 16th Design Automation Conference
A Wire-Routing Scheme Based on Trunk-Division Methods
IEEE Transactions on Computers
A Wire-Routing Scheme Based on Trunk-Division Methods
IEEE Transactions on Computers
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This paper describes the layout model and algorithm applied to an advanced LILAC system which is capable of automatically designing MOS/LSI chip layouts containing PLAs. The system, which is a fully automated design system, inputs logic description and outputs layout drawing.