Methods for hierarchical automatic layout of custom LSI circuit masks
DAC '78 Proceedings of the 15th Design Automation Conference
An optimum channel-routing algorithm for polycell layouts of integrated circuits
DAC '73 Proceedings of the 10th Design Automation Workshop
LTX - a system for the directed automatic design of LSI circuits
DAC '76 Proceedings of the 13th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
A high quality, low cost router for MOS/LSI
DAC '72 Proceedings of the 9th Design Automation Workshop
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Floss: An approach to automated layout for high-volume designs
DAC '77 Proceedings of the 14th Design Automation Conference
An hierarchical language for the structural description of digital systems
DAC '77 Proceedings of the 14th Design Automation Conference
Advanced LILAC - an Automated Layout Generation system for MOS/LSIs
DAC '74 Proceedings of the 11th Design Automation Workshop
Reducing channel density in standard cell layout
DAC '83 Proceedings of the 20th Design Automation Conference
Linear ordering and application to placement
DAC '83 Proceedings of the 20th Design Automation Conference
The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing
DAC '81 Proceedings of the 18th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
The benefits of external wires in single row routing
Information Processing Letters
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CALMOS (Computer Aided Layout of MOS) is a computer system for the layout of custom MOS/LSI circuits. Starting with a standard cell library and a simple circuit connectivity description, the program performs various automatic and/or interactive procedures such as initial placement, assignment of equivalent and equipotential pins, optimization of the placement, prerouting, routing, routing compression, fan in fan out and crosstalk verification and circuit verification. The database has reentrant properties such that a designer can step through the system and try out different possibilities. After each step the results are immediately available and can be compared with previous outputs. This on-line optimization avoids multiple rerunning of the task and will also yield a better chip minimization.