An optimum channel-routing algorithm for polycell layouts of integrated circuits

Authors:
B. W. Kernighan;D. G. Schweikert;G. Persky
Affiliations:
-;-;-
Venue:
DAC '73 Proceedings of the 10th Design Automation Workshop
Year:
1973

Citing 3
Cited 34

A high quality, low cost router for MOS/LSI

DAC '72 Proceedings of the 9th Design Automation Workshop
Wire routing by optimizing channel assignment within large apertures

DAC '71 Proceedings of the 8th Design Automation Workshop
A solution to line-routing problems on the continuous plane

DAC '69 Proceedings of the 6th annual Design Automation Conference

Abstract routing of logic networks for custom module generation

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Strip layout: a new layout methodology for standard circuit modules

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
PLAY: pattern-based symbolic cell layout: Part I: transistor placement

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A “DOGLEG” channel router

25 years of DAC Papers on Twenty-five years of electronic design automation
The chip layout problem: an automatic wiring procedure

25 years of DAC Papers on Twenty-five years of electronic design automation
A “GGreedy” channel router

25 years of DAC Papers on Twenty-five years of electronic design automation
Hierarchical channel router

25 years of DAC Papers on Twenty-five years of electronic design automation
An Efficient Channel Routing Algorithm to Yield an Optimal Solution

IEEE Transactions on Computers
Improved channel routing by via minimization and shifting

DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Comparative router performance

ACM SIGDA Newsletter
Hierarchical channel router

DAC '83 Proceedings of the 20th Design Automation Conference
A topology for semicustom array-structured LSI devices, and their automatic customisation

DAC '83 Proceedings of the 20th Design Automation Conference
Aiming at a general routing strategy

DAC '81 Proceedings of the 18th Design Automation Conference
A preprocessor for channel routing

DAC '81 Proceedings of the 18th Design Automation Conference
A dogleg “optimal” channel router with completion enhancements

DAC '81 Proceedings of the 18th Design Automation Conference
CELTIC - solving the problems of LSI design with an integrated polycell DA system

DAC '81 Proceedings of the 18th Design Automation Conference
Methods for hierarchical automatic layout of custom LSI circuit masks

DAC '78 Proceedings of the 15th Design Automation Conference
A “grid-free” channel router

DAC '80 Proceedings of the 17th Design Automation Conference
PRO - an automatic string placement program for polycell layout

DAC '76 Proceedings of the 13th Design Automation Conference
A “Dogleg” channel router

DAC '76 Proceedings of the 13th Design Automation Conference
An approximation algorithm for manhattan routing

STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
The siemens-avesta-system for computer-aided design of MOS-standard cell circuits

DAC '77 Proceedings of the 14th Design Automation Conference
A class of min-cut placement algorithms

DAC '77 Proceedings of the 14th Design Automation Conference
The chip layout problem: An automatic wiring procedure

DAC '77 Proceedings of the 14th Design Automation Conference
A minimum-impact routing algorithm

DAC '82 Proceedings of the 19th Design Automation Conference
A “greedy” channel router

DAC '82 Proceedings of the 19th Design Automation Conference
Advanced LILAC - an Automated Layout Generation system for MOS/LSIs

DAC '74 Proceedings of the 11th Design Automation Workshop
CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI

DAC '79 Proceedings of the 16th Design Automation Conference
Comments on "An Optimal Solution for the Channel-Assignment Problem"

IEEE Transactions on Computers
A Wire-Routing Scheme Based on Trunk-Division Methods

IEEE Transactions on Computers
A Wire-Routing Scheme Based on Trunk-Division Methods

IEEE Transactions on Computers
Optimal Wiring of Movable Terminals

IEEE Transactions on Computers
Influence on LSI package wireability of via availability and wiring track accessibility

IBM Journal of Research and Development
Algorithms for permutation channel routing

Integration, the VLSI Journal

Quantified Score

Hi-index	0.01

Visualization

Abstract

This paper presents an algorithm for finding optimum routings for interconnection paths in a channel between two parallel rows of circuit cells. The algorithm, although based on branch and bound, has provided optimum routings for circuits with 50 to 60 nets in a minute or two of computing.