Two probabilistic results on rectilinear Steiner trees
STOC '86 Proceedings of the eighteenth annual ACM symposium on Theory of computing
Decomposition of logic networks into silicon
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Introduction to VLSI Systems
Cell compilation with constraints
DAC '84 Proceedings of the 21st Design Automation Conference
An algorithm for searching shortest path by propagating wave fronts in four quadrants
DAC '81 Proceedings of the 18th Design Automation Conference
A multi-pass, multi-algorithm approach to PCB routing
DAC '78 Proceedings of the 15th Design Automation Conference
An optimum channel-routing algorithm for polycell layouts of integrated circuits
DAC '73 Proceedings of the 10th Design Automation Workshop
PRO - an automatic string placement program for polycell layout
DAC '76 Proceedings of the 13th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Cellular wiring and the cellular modeling technique
DAC '69 Proceedings of the 6th annual Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
An iterative-improvement penalty-function-driven wire routing system
IBM Journal of Research and Development
An algorithm for improving optimal placement for river-routing
EURO-DAC '91 Proceedings of the conference on European design automation
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This paper describes a switchbox-type router for custom VLSI module generation as performed by a module planner. A module is decomposed into abstract cells consisting of global routes and Boolean functional specifications. Each abstract cell is given to a cell synthesizer which generates the circuit layout and through-the-cell routing. Abstract routing for a module planner is in some sense similar to switchbox routing to the degree that all of the routes are generated internally within a rectangular boundary (routes are coming from four sides). The principle difference with respect to standard switchbox routing is at the geometric level, where a cell synthesizer generates the routing conduction layers along with circuit devices for each abstract cell within this rectangular region. The aspects of this paper which are thought to be novel contributions are 1) a relative pin assignment algorithm for the abstract cells; 2) a global routing penalty function which not only considers previous routes, but also considers gate complexity within the cells; 3) an efficient optimization algorithm for minimizing the number of tracks running through the module.