Introduction to VLSI Systems
Pictures with parentheses: Combining graphics and procedures in a VLSI layout tool
DAC '83 Proceedings of the 20th Design Automation Conference
APSS: An automatic PLA synthesis system
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
HOPLA-PLA optimization and synthesis
DAC '83 Proceedings of the 20th Design Automation Conference
Internal connection problem in large optimized PLAs
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Techniques for programmable logic array folding
DAC '82 Proceedings of the 19th Design Automation Conference
PAOLA: A tool for topological optimization of large PLAS
DAC '82 Proceedings of the 19th Design Automation Conference
Abstract routing of logic networks for custom module generation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Improving a PLA area by pull-up transistor folding
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Decomposition of logic networks into silicon
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
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This paper describes a cell compiler that translates cell descriptions given in form of Boolean equations including pass transistors into layout descriptions in Caltech Intermediate Form (CIF). The translation process is constrained by given height and width of the cell and the position of each I/O signal on the boundary of the cell. Furthermore, the size of each transistor as well as power consumption can be arbitrarily chosen. This cell compiler allows routing through the cell in any direction. The cell architecture is based on PLA structures.