Computer Logic, Testing and Verification
Computer Logic, Testing and Verification
Introduction to VLSI Systems
An Algorithm for Optimal PLA Folding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Lower Overhead Design for Testability of Programmable Logic Arrays
IEEE Transactions on Computers - The MIT Press scientific computation series
A parallel PLA minimization program
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
25 years of DAC Papers on Twenty-five years of electronic design automation
A defect-tolerant and fully testable PLA
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A heuristic algorithm for PLA block folding
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A new integrated system for PLA testing and verification
DAC '83 Proceedings of the 20th Design Automation Conference
APSS: An automatic PLA synthesis system
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
Optimum reduction of programmable logic array
DAC '83 Proceedings of the 20th Design Automation Conference
HOPLA-PLA optimization and synthesis
DAC '83 Proceedings of the 20th Design Automation Conference
Cell compilation with constraints
DAC '84 Proceedings of the 21st Design Automation Conference
A branch and bound algorithm for optimal pla folding
DAC '84 Proceedings of the 21st Design Automation Conference
Microassembly and area reduction techniques for PLA microcode
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
A Testable PLA Design with Low Overhead and High Fault Coverage
IEEE Transactions on Computers
Lower overhead design for testability of programmable logic arrays
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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The optimal PLA folding problem is presented and discussed in its different forms. In particular, new algorithms for row folding in unconstrained architectures and in AND-OR-AND architectures are presented and their complexity examined. The problem of finding an optimal row folding after a column folding has been performed, is described and an algorithm for its solution given. Finally, the organization of an APL package for row and column folding of PLA's is introduced and experimental results reported.