Optimum reduction of programmable logic array

Authors:
T. C. Hu;Y. S. Kuo
Affiliations:
Department of Electrical Engineering and Computer Sciences, University of California, San Diego, La Jolla, California;Department of Electrical Engineering and Computer Sciences, University of California, San Diego, La Jolla, California
Venue:
DAC '83 Proceedings of the 20th Design Automation Conference
Year:
1983

Citing 4
Cited 2

Combinatorial Algorithms

Combinatorial Algorithms
A depth-first branch-and-bound algorithm for optimal PLA folding

DAC '82 Proceedings of the 19th Design Automation Conference
Optimal bipartite folding of PLA

DAC '82 Proceedings of the 19th Design Automation Conference
Techniques for programmable logic array folding

DAC '82 Proceedings of the 19th Design Automation Conference

Design of repairable and fully diagnosable folded PLAs for yield enhancement

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A heuristic algorithm for PLA block folding

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

We consider the optimum PLA column folding problem where vertices in the column intersection graph are first partitioned into two parts. Both upper and lower bounds on the size of the folding are given in terms of the number of edges and vertices in the bipartite graph G. Efficient polynomial optimum algorithms are given for the case that G is a tree and other cases. A heuristic algorithm with error bound is given for a general bipartite graph. A new graph model is introduced. We also study one-cut bipartite folding, AND-OR-AND row folding, and the general partitioning problem.